An ASIC Low Power Primer by Rakesh Chadha & J. Bhasker

Author:Rakesh Chadha & J. Bhasker
Language: eng
Format: epub
Publisher: Springer New York, New York, NY

This technique is also referred to as adaptive voltage scaling (AVS).

6.4 Dynamic Voltage and Frequency Scaling

Dynamic voltage and frequency scaling (DVFS) dynamically adapts voltage and frequency for different blocks. Look-up tables or on-chip monitors are used to adjust voltage and frequency depending upon performance requirements. Speed ­degradation or reducing the frequency of a block allows a lower voltage to be applied, which results in lower power. Alternately, a higher operating voltage leads to higher power and allows for increased performance. Notice that power is a function of the square of the voltage. Thus, reducing the voltage has a significant impact on power.

A design would typically have multiple functional modes—high speed mode and a lower performance mode. The design implementation is targeted for high performance. During the time the design is not operating at full performance, the power supply is reduced to account for reduced performance.

Significant power savings can be achieved using this approach, though it is expensive in terms of architectural design, verification and implementation. The impact on area and timing is minimal.

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